Design and Experimentation of Inductorless Low-Pass NGD Integrated Circuit in 180-nm CMOS Technology

This article introduces an innovative design of a low-pass (LP) negative group delay (NGD) integrated circuit (IC) in the 180-nm CMOS technology. The LP-NGD is inductorless topology constituted by RC-network with metal-insulator-metal (MIM) capacitor and polygate resistor. methodology illustrated considering chip layout process. Then, first run simulation performed rule check (DRC) 2.5 mm ${\times }$ 2.2 versus schematic (LVS) approaches. feasibility IC implementation validated chip-onboard (CoB). proof concept (PoC) miniaturized was tested both S-parameter time domain (TD). As expected, calculated, simulated, experimented results CoB showing NGD about ?10 ns over 12 MHz dB attenuation are confirmed. active technology compensates insertion loss to 2.4 dB, GD reaches ?11 ns, reflection ?20 dB. Moreover, TD investigations were also show generating pulse arbitrary waveform signal advance through designed fabricated prototypes.